This relates to integrated circuits such as programmable integrated circuits with interconnect circuitry.
Programmable integrated circuits are well known. Programmable integrated circuits can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design (CAD) tools to design a custom logic circuit. When the design process is complete, the tools generate configuration data. The configuration data is loaded into programmable integrated circuit memory elements to configure the device to perform the functions of the custom logic circuit. In particular, the configuration data configures programmable interconnects, programmable routing circuits, and programmable logic circuits in the programmable integrated circuits.
Programmable integrated circuits include programmable logic circuits that are configured to receive input signals and perform custom functions to produce output signals. The input and output signals of each logic circuit are provided by interconnects that can be configured to route selected signals throughout the programmable integrated circuit.
Programmable integrated circuits often operate using clock signals that operate at clock frequencies. To accommodate increasing performance requirements of modern programmable integrated circuits, clock frequencies are often increased. The maximum clock frequency at which circuitry on a programmable integrated circuit can operate is inversely proportional to the maximum delay between any two registers that share a clock signal (sometimes referred to as the critical path delay). If the maximum delay is decreased, the clock frequency can be increased, which tends to improve system performance.
Interconnect delay contributes to the critical path delay between registers. The signal delay associated with a given interconnect is proportional to the length of the interconnect. In order to reduce the maximum delay between first and second registers, circuit designers often route signals through additional registers of programmable logic circuits that are interposed between the first and second registers (e.g., to reduce the length of interconnects traversed by a signal from the output of any given register to the input of a subsequent register). The technique of routing signals through additional registers to reduce critical path length may sometimes be referred to as pipelining or register pipelining. Registers used for pipelining are sometimes referred to as pipeline registers.
Using registers of conventional programmable logic circuits for pipelining introduces additional delay that reduces the performance benefits provided by pipelining. For example, conventional programmable logic circuits have input multiplexers and look-up table circuitry through which signals are routed to reach programmable logic circuits for processing. The input multiplexers are coupled to many interconnects (e.g., tens or hundreds or more). In this scenario, it may be time consuming for the input multiplexers to select a signal from a single interconnect to route through the look-up table circuitry to the registers. The signal also occupies an input terminal of the programmable logic circuits, which reduces the number of available input terminals of the programmable logic circuits that can be used to perform custom user functions.